1. Field of the Invention
The present invention relates to a ΔΣ analog-to-digital converter, and particularly to a ΔΣ analog-to-digital converter separately provided with an amplifier in the previous stage of a conversion circuit.
2. Description of Related Art
Along with the progress of the digital circuit technology, input analog signals are becoming to be processed by digital circuits. In such case, the input analog signals must be converted into digital signals. Therefore, there are many analog-to-digital converters suggested. One of the analog-to-digital converters is a ΔΣ analog-to-digital converter. The ΔΣ analog-to-digital converter has a characteristic of an excellent noise shaping ability to reduce a noise component overlapped to an analog signal. The noise shaping ability of the ΔΣ analog-to-digital converter improves by an order.
The ΔΣ analog-to-digital converter is formed of multiple stages of integrator circuits, where the integrator circuit is formed of a capacitor and an amplifier. The number of the stages is determined by the order of the ΔΣ analog-to-digital converter. Further, the number of the amplifiers and capacitors in the ΔΣ analog-to-digital converter increases in proportion to the order. Therefore, there is a problem in the ΔΣ analog-to-digital converter that the circuit size increases according to the order. An example of the technique to suppress the circuit size of the ΔΣ analog-to-digital converter is disclosed in Japanese Unexamined Patent Application Publication No. 9-205369 and Domestic Re-publication of PCT International Publication for Patent Application, No. WO 96/25800.
The ΔΣ analog-to-digital converters disclosed in Japanese Unexamined Patent Application Publication No. 9-205369 and Domestic Re-publication of PCT International Publication for Patent Application, No. WO 96/25800 have multiple capacitors connected in parallel to a feedback path of one amplifier. Then, the multiple capacitors are switched in a time-sharing manner to perform an integration operation. That is, the ΔΣ analog-to-digital converter disclosed in Japanese Unexamined Patent Application Publication No. 9-205369 and Domestic Re-publication of PCT International Publication for Patent Application, No. WO 96/25800 forms a converter by a smaller number of amplifiers than the order. This enables to reduce the circuit area and power consumption for the amplifiers.